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P4C174 - HIGH SPEED 8K x 8 CACHE TAGE STATIC RAM

Datasheet Summary

Description

The P4C174 is a 65,536 bit high speed cache tag static RAM organized as 8K x 8.

The CMOS memory has equal access and cycle times.

Inputs are fully TTL-compatible.

Features

  • High Speed Address-To-Match - 8 ns Maximum Access Time High-Speed Read-Access Time.
  • 8/10/12/15/20/25 ns (Commercial).
  • 15/20/25 ns (Military) Open Drain MATCH Output Reset Function 8-Bit Tag Comparison Logic Automatic Powerdown During Long Cycles P4C174 HIGH SPEED 8K X 8 CACHE TAGE STATIC RAM Data Retention at 2V for Battery Backup Operation Advanced CMOS Technology Low Power Operation Package Styles Available.
  • 28 Pin 300 mil DIP.

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Datasheet preview – P4C174

Datasheet Details

Part number P4C174
Manufacturer PYRAMID
File Size 639.88 KB
Description HIGH SPEED 8K x 8 CACHE TAGE STATIC RAM
Datasheet download datasheet P4C174 Datasheet
Additional preview pages of the P4C174 datasheet.

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Full PDF Text Transcription

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FEATURES High Speed Address-To-Match - 8 ns Maximum Access Time High-Speed Read-Access Time – 8/10/12/15/20/25 ns (Commercial) – 15/20/25 ns (Military) Open Drain MATCH Output Reset Function 8-Bit Tag Comparison Logic Automatic Powerdown During Long Cycles P4C174 HIGH SPEED 8K X 8 CACHE TAGE STATIC RAM Data Retention at 2V for Battery Backup Operation Advanced CMOS Technology Low Power Operation Package Styles Available — 28 Pin 300 mil DIP — 28 Pin 300 mil Plastic SOJ Single Power Supply — 5V±10% DESCRIPTION The P4C174 is a 65,536 bit high speed cache tag static RAM organized as 8K x 8. The CMOS memory has equal access and cycle times. Inputs are fully TTL-compatible. The cache tag RAMs operate from a single 5V±10% power supply.
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