FEATURES
Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 12/15/20/25/35 ns (Industrial) – 15/20/25/35/45 ns (Military) Low Power Operation (Commercial/Military) Output Enable and Dual Chip Enable Functions 5V ± 10% Power Supply Data Retention with 2.0V Supply, 10 µA Typical Current (P4C1981L/1982L Military) Separate Inputs and Outputs – P4C1981/L Input Data at Outputs during Write – P4C1982/L Outputs in High Z during Write Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil DIP, SOJ – 28-Pin 350 x 550 mil LCC – 28-Pin CERPACK DESCRIPTION
The P4C1981/L and P4C1982/L are 65,536-bit (16Kx4) ultra high-speed static RAMs similar to the P4C198, but with separate data I/O pins. The P4C1981/L feature a transparent write operation when OE is low; the outputs of the P4C1982/L are in high impedance during the write cycle. All devices have low power standby modes. The RAMs operate from a single 5V ± 10% tolerance power supply.
PYRAMID
