P4C423 Datasheet | PYRAMID

FEATURES High Speed (Equal Access and Cycle Times) - 10/12/15/20/25/35 ns (mercial) - 15/20/25/35 ns (Military) CMOS for Low Power - 495 m W Max. - 10/12/15/20/25 (mercial) - 495 m W Max. - 15/20/25/35 (Military) Single 5V±10% Power Supply Separate I/O Fully TTL patible Inputs and Outputs Resistant to single event upset and latchup resulting from advanced process and design improvements Standard 24-pin 300 mil DIP package. DESCRIPTION The P4C423 is a 1,024-bit high-speed (10ns) Static RAM with a 256 x 4 organization. The memory requires no clocks or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL patible. Operation is from a single 5 Volt supply. Easy memory expansion is provided by an active LOW chip select one (CS1) and active HIGH chip select two (CS2) as well as 3-state outputs. In addition to high performance and high density, the device features latch-up protection, single event and upset protection. The P4C423 is offered in a 24-pin 300 mil DIP. Devices are offered in both mercial and military temperature ranges. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DIP (C4) Document # SRAM108 REV OR Revised October 2005 MAXIMUM RATINGS(1) Symbol Parameter VCC Power Supply Pin with Respect to GND VTERM Terminal Voltage with Respect to GND (up to 7.0V) TA Operating Temperature Value Unit - 0.5 to +7 V - 0.5 to VCC +0.5 - 55 to +125 °C REMENDED OPERATING CONDITIONS Grade (2) mercial Military Ambient Temp 0°C to 70°C - 55°C to 125°C Gnd Vcc 0V 5.0V ±10% 0V 5.0V ±10% Symbol Parameter TBIAS...