PACE1753-SOS Datasheet PDF

FEATURES

Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory (10,240 bits) for both the MMU and BPU functions are included on the chip. Designed to interface memory to the PACE1750A/AE. Provides the following additional functions: — EDAC, Error Detection and Correction—or parity generation and detection — Correct data register—for diagnostics — First memory failing address register — Illegal address error detection— programmable — Multi-Master arbitration 8-bit extended address laches and drivers on chip. 20, 25 and 30 MHz operation over the Military Temperature Range Single 5V ± 10% Power Supply Available with Class S manufacturing, screening, and testing. SOS Insulated substrate latch-up immunity and excellent SEU tolerance. SOS devices are fully interchangeable with applicat