FEATURES
Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory (10,240 bits) for both the MMU and BPU functions are included on the chip. Designed to interface memory to the PACE1750A/AE 16-bit, 40 MHz processor. Systems can be designed where no WAIT states are required up to 40 MHz clock rates when using these PACE products. System performance and device count are optimized when used with the PACE1754 Processor Interface Circuit (PIC). Provides the following additional functions: — EDAC, Error Detection and Correction—or parity generation and detection — Correct data register—for diagnostics — First memory failing address register MEMORY MANAGEMENT UNIT AND BLOCK PROTECT UNIT “COMBO” — FUNCTIONAL DESCRIPTION
PYRAMID
