PYA28C64B
PYA28C64B is STATIC CMOS RAM manufactured by PYRAMID.
FEATURES
Access Times of 150, 200, 250 and 350ns
Single 5V±10% Power Supply
Simple Byte and Page Write
Low Power CMOS:
- 40 m A Active Current
- 100 µA Standby Current
Fast Write Cycle Times
8K x 8 EEPROM
Software Data Protection CMOS & TTL patible Inputs and Outputs Endurance:
- 100,000 Write Cycles Data Retention: 10 Years Available in the following packages:
- 28-Pin 600 mil Ceramic DIP
- 32-Pin Ceramic LCC (450x550 mils)
DESCRIPTION
The PYA28C64B is a 5 Volt 8Kx8 EEPROM. The device supports 64-byte page write operation. The PYA28C64B features
DATA and Toggle Bit Polling to indicate early pletion of a Write Cycle. The device also includes user-optional software data protection. Data Retention is 10 Years. The device is available in a 28-Pin 600 mil wide Ceramic DIP and 32-Pin LCC.
Functional Block Diagram
Pin Configuration
Document # EEPROM111 REV 02
DIP (C5-1)
LCC (L6) Modified April 2015
- 8K x 8 EEPROM
OPERATION
READ Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
BYTE WRITE Write operations are initiated when both CE and WE are LOW and OE is HIGH. The PYA28C64B supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to pletion.
PAGE WRITE The page write feature of the PYA28C64B allows 1 to 64 bytes of data to be consecutively written to the PYA28C256 during a single internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address),...
