PJDLC05C-03 Datasheet | PanJit Semiconductor

FEATURES - Maximum capacitance @ 0 Vdc Bias of 1.0 p F between terminals 1-3 or terminals 2-3 - IEC61000-4-2 esd 15k V Air, 8k V contact pliance - In pliance with EU Ro HS 2002/95/EC directives 0.004(0.10)MAX. MECHANICAL DATA - Case: SOT-23, plastic - Terminals: solderable per MIL-STD-750, Method 2026 - Approx. Weight: 0.0003 ounce, 0.0084 gram - Marking : DBA Fig.21 MAXIMUM RATINGS Parameter Op e r a ti ng J unc ti o n S to r a g e Te mp e ra tur e Ra ng e Symbol TJ T S TG Value -55 to +150 -55 to +150 Units ELECTRICAL CHARACTERISTICS PJDLC05C-03 Parameter Reverse Stand-Off Voltage Symbol VRWM VBR IR CJ I PP VC Conditions I T=1m A VRWM = 5V, T = 25OC Between pin1.2 to 3 VR=0V,f=1MHz t P=8/20 μsec t P=8/20 μsec Minimum 6 Typical Maximum 5 20 1.0 12 22 Units V V μA p F A V .. Reverse Breakdown Voltage Reverse Leakage Current Junction Capacitance Peak Pulse Current Max Clamping Voltage February 16,2011-REV.01 PAGE . 1 0.80 0.70 Capacitance, CJ, p F Peak Pulse Current Ipp, A 0.60 0.50 0.40 0.30 0.20 0.10 0.00 0 2 4 6 14 12 10 8 6 4 2 0 6 8 10 12 14 16 18 20 22 Reverse Bias Voltage VR, V Clamping Voltage VC, V Fig.1 TYPICAL CAPACITANCE Fig.2 PULSE WAVE FORM 50% of Ipp @20ms Rise time 10-90% - 8ms Fig .3 PULSE WAVE FORM .. February 16,2011-REV.01 PAGE . 2 MOUNTING PAD...