PI6CV855 Datasheet | Pericom Semiconductor

Features • PLL clock distribution optimized for SSTL_2 DDR SDRAM applications. • Distributes one differential clock input pair to five differential clock output pairs. • Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 • Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 • External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input. • Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.5V for differential output drivers • Available Package: – Plastic 28-pin TSSOP Product Description PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM applications. This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to five differential pairs of clock outputs (Y[0:4], Y[0:4]) and one differential pair feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the Analog Power input (AVDD). When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. When the input frequency falls below a suggested detection frequency that is below the operating frequency of the PLL, the device will enter a low power mode. In low power mode, PLL is turned OFF, Y[0:4] and Y[0:4] outputs are 3-stated. The PI6CV855 is able to track Spread Spectrum Clocking to reduce EMI. Block Diagram Pin Configuration Y0 Y0 CLK CLK FBIN FBIN GND Y0 Y0 VD D Q CLK CLK AV D D AG N D GND Y1 Y1 VD D Q Y2 Y2 1 2 3 4 5 6 8 9 10 11 12 13 14 28 27 26 25 24 Y4 Y4 VD D Q GND FBOUT FBOUT VD D Q FBIN FBIN GND VD D Q Y3 Y3 GND Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 28-Pin 23 L 22 7 21 20 19 18 17 16 15 AVDD Logic and Test Ciruit PS8545 06/20/01 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890...