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PI6CV855 - PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory

General Description

PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM applications.

This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels.

Key Features

  • • PLL clock distribution optimized for SSTL_2 DDR SDRAM.

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Other Datasheets by Pericom Semiconductor (now Diodes Incorporated)

Part Number Description
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory Product Features • PLL clock distribution optimized for SSTL_2 DDR SDRAM applications. • Distributes one differential clock input pair to five differential clock output pairs. • Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 • Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 • External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input. • Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.