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PI3VDP1413A - DisplayPort 3.4Gb/s Level Shifter/Redriver

This page provides the datasheet information for the PI3VDP1413A, a member of the PI3VDP1431 DisplayPort 3.4Gb/s Level Shifter/Redriver family.

Datasheet Summary

Description

TQFN(32) 3x6mm DDC Switch TQFN(32) 3x6mm DDC Buffer Note: Please refer ordering addendum at the end of the datasheet Pin Configuration SDA_SINK HPD_SINK OEB GND GND Description PI3VDP1431 is a low power dual-mode DisplayPort Level Shifter with intergrated 3.4Gbps redriver to improve jitter perfo

Features

  • ÎÎDual-mode DisplayPort level shifter/Redriver ÎÎOperation up to 3.4 Gbps per lane (340MHz pixel clock) ÎÎ4K Ultra HD, 3D video formats (1080p, 1080i, 720p), 48-bit per pixel Deep Color support ÎÎLow standby current with DDC passive Switch or Buffer mode ÎÎFlexible 3 steps equalization control steps: 2.5, 5, 7.5 dB ÎÎPre-emphasis control 3 steps: 0, 1.5, 2.5 dB ÎÎAutomatic output squelch and HPD function for power saving states management at no input signal condition ÎÎConvert low-swing DC or AC.

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Datasheet preview – PI3VDP1413A

Datasheet Details

Part number PI3VDP1413A
Manufacturer Pericom Semiconductor
File Size 792.45 KB
Description DisplayPort 3.4Gb/s Level Shifter/Redriver
Datasheet download datasheet PI3VDP1413A Datasheet
Additional preview pages of the PI3VDP1413A datasheet.

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Full PDF Text Transcription

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COMPANY CONFIDENTIAL PI3VDP1431 PI3VDP1413A Low Power Dual-mode DisplayPort 3.4Gb/s Level Shifter/Redriver Features ÎÎDual-mode DisplayPort level shifter/Redriver ÎÎOperation up to 3.4 Gbps per lane (340MHz pixel clock) ÎÎ4K Ultra HD, 3D video formats (1080p, 1080i, 720p), 48-bit per pixel Deep Color support ÎÎLow standby current with DDC passive Switch or Buffer mode ÎÎFlexible 3 steps equalization control steps: 2.5, 5, 7.5 dB ÎÎPre-emphasis control 3 steps: 0, 1.5, 2.5 dB ÎÎAutomatic output squelch and HPD function for power saving states management at no input signal condition ÎÎConvert low-swing DC or AC coupled differential input ÎÎIntegrated DDC level shifter or DDC Buffer (A version) ÎÎSignal Input channels with pull-down termination resistor ÎÎ3.
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