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PI6CEQ20200 Datasheet Gen2 / Gen3 Buffer

Manufacturer: Pericom Semiconductor (now Diodes Incorporated)

General Description

The PI6CEQ20200 is a high performance PCIe Gen2/ Gen3 zero delay buffer with two HCSL outputs.

Peri’s proprietary equalization technique used in this device improves signal integrity and makes this device suitable for PCIe Gen2/ Gen3 applications even when the input from the main clock has to travel a long distance.

Pin Configuration (20-Pin TSSOP & 20-Pin QSOP) SRCIN SRCIN# EQ PLL_BW_SEL SCLK SDATA Control PLL OE0# CLK0 CLK0# OE1# CLK1 CLK1# PLL_BW_SEL SRCIN SRCIN# OE_0# VDD GND CLK0 CLK0# VDD SDATA 1 2 3 4 5 6 7 8 9 10 20 VDDA 19 GNDA 18 IRef 17 OE_1# 16 VDD 15 GND 14 CLK1 13 CLK1# 12 VDD 11 SCLK 15-0058 1 .peri.

Key Features

  • ÎÎPCIe Gen2/ Gen3.
  • compliant clock buffer/ZDB.
  • Gen3 performance only available in Commercial temp ÎÎInternal equalization for better signal integrity ÎÎ2 HCSL outputs ÎÎDual PLL bandwidth for SSC tracking ÎÎCycle-to-Cycle Jitter : 40ps (typ) ÎÎOutput-to-Output Skew.

PI6CEQ20200 Distributor