Datasheet Summary
Features
ÎÎPCIe Gen2/ Gen3- pliant clock buffer/ZDB
- Gen3 performance only available in mercial temp
ÎÎInternal equalization for better signal integrity ÎÎ2 HCSL outputs ÎÎDual PLL bandwidth for SSC tracking ÎÎCycle-to-Cycle Jitter : 40ps (typ) ÎÎOutput-to-Output Skew <10ps ÎÎ3.3V supply voltage ÎÎTSSOP-20 packages
Applications
ÎÎServers ÎÎEmbedded puting systems ÎÎNetworking systems
Block Diagram
PCIe® Gen2 / Gen3 Buffer
Description
The PI6CEQ20200 is a high performance PCIe Gen2/ Gen3 zero delay buffer with two HCSL outputs. Peri’s proprietary equalization technique used in this device improves signal integrity and makes this device suitable for PCIe Gen2/ Gen3...