Pericom Semiconductor PI6C5930
The PI6C5930 clock driver uses a PLL (phase-locked loop) to reduce time skew between a reference clock input (SYNC) and the outputs. This driver generates six clock outputs: Q0 through Q4 running at the same frequency, plus Q/2 which runs at one half the frequency of Q0-Q4. When FREQ_SEL = HIGH, applying either one of the Q0-Q4 outputs to the FEEDBACK pin results in five copies of the reference input.| Part No. | PI6C5930 |
|---|---|
| Datasheet | PI6C5930 Download |
| Manufacturer |  Pericom Semiconductor |
| Description | Low Skew CMOS PLL Clock Driver |
| Buy | Stock & Price |
FEATURES
● Wide frequency range: 100 MHz max.● Five Q and one Q/2 outputs
● Output skew < 250ps (rising edges)
● Internal RC loop filter network
● Low noise TTL-compatible outputs
● Balanced drive outputs: +24mA
● Outputs Hi-Z and registers reset when OE = LOW
● PLL bypass for testing and low-frequency applications
● Small footprint 20-pin QSOP package (Q)
DESCRIPTION
An internal loop filter eliminates the need for external compensation. Thanks to design improvements, the PI6C5930 is capable of generating highly stable frequencies up to 100 MHz, while maintaining less than 250 ps skew between outputs. If Q/2 is applied to the FEEDBACK pin, five clocks at double the reference input are created. The output enable (OE) function may be used to turn all outputs off and save power. The FREQ_SEL input is set to LOW if the SYNC frequency is lower than 30 MHz, otherwise it should be set HIGH. The PLL_EN function can be used for testing and to bypass the PLL in low frequency applications. Block...
