PLL102-04 - Low Skew Output Buffer

Product Overview

PhaseLink Corporation

Datasheet Details

Part number	PLL102-04
Manufacturer	PhaseLink Corporation
File Size	269.36 KB
Description	Low Skew Output Buffer
Datasheet	PLL102-04 Datasheet
Additional preview pages of the PLL102-04 datasheet.

Product details

Description

The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package.

It has four outputs that are synchronized with the input.

The synchronization is established via CLKOUT feed back to the input of the PLL.

Features

Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).
Zero input - output delay.
Less than 700 ps device - device skew.
Less than 250 ps skew between outputs. www. DataSheet4U. com.
Less than 200 ps cycle - cycle jitter.
Output Enable function tri-state outputs.
3.3V operation.
Available in 8-Pin 150mil SOIC.

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Other Datasheets by PhaseLink Corporation

PLL102-03 - Low Skew Output Buffer
PLL102-05 - Low Skew Output Buffer
PLL102-10 - Low Skew Output Buffer
PLL102-108 - Programmable DDR Zero Delay Clock Driver
PLL102-109 - Programmable DDR Zero Delay Clock Driver
PLL102-15 - Low Skew Output Buffer

Published: Oct 28, 2008 |