PLL103-07 Overview
“True” clocks of differential pair outputs. “plementary” clocks of differential pair outputs. The bytes must be accessed in sequential order from lowest to highest byte.
PLL103-07 Key Features
- Generates 12-output buffers from one input
- Supports VIA Pro266 DDR chipset
- Supports up to 2 DDR DIMMS
- Supports up to 400MHz DDR, SDRAMS
- One additional output for feedback
- 6 differential clock distribution
- Less than 5ns delay
- Skew between any outputs is less than 100 ps
- 2.5V Supply range
- Available in 28-pin SSOP