PLL130-05 Datasheet | PhaseLink Corporation

FEATURES - - - - - Differential PECL output Single AC coupled input (min. 100m V swing). Input range from DC to 1.0 GHz. 2.5V to 3.3V operation. Available in 3x3mm QFN. GND GND .. PIN CONFIGURATION (TOP VIEW) 13 14 15 16 8 7 6 5 PECL_BAR VDD PECL GND 1 2 3 4 GND OE DESCRIPTION The PLL130-05 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.3GHz. It provides one pair of differential PECL outputs. Any input signal with at least 100m V swing can be used as reference signal. This chip is ideal for conversion from sine wave, TTL, CMOS, or LVDS to PECL. REF_IN Note: V denotes internal pull down BLOCK DIAGRAM REF_IN Input PECL_BAR PECL Amplifier 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 .phaselink. Rev 09/09/04 Page 1 High Speed Translator Buffer to PECL (Enable Low) PIN DESCRIPTIONS Name GND VDD REF_IN PECL PECL_BAR .. 3x3mm QFN Pin number 1,2,4,5, 9,13,14,15 7,10,11,12 3 6 8 16 Type P P I O O I Ground. Description Power supply. Reference input signal. The frequency of this signal will be reproduced at the output (after translation to PECL level). PECL True output. PECL plementary output. Output enable (‘0’ for enable). Internal pull-down (default is ‘0’). ELECTRICAL...