PLL520-09 Description
Frequency control input (0.3V to 3.0V) Ground (except pin 12 on PLL520-06: This pin has an internal pull-up that will default DRIVSEL to ‘1’ when not connect to GND. CMOS output of PLL520-06 will be high drive CMOS when DRIVSEL is set to ‘0’, and will be standard CMOS otherwise.
PLL520-09 Key Features
- 100MHz to 200MHz Fundamental Mode Crystal. Output range: 100
- 200MHz (no multiplication), 200
- 400MHz (2x multiplier), 400
- 800MHz (4x multiplier), or 800MHz
- GND/DRIVSEL
- 3x3mm QFN- Pin number