PLL52C59-14A Datasheet | PhaseLink

System Clock Generator with Integrated Buffers Features n Generates all clock frequencies for Pentium, CYRIX and AMD CPU. n Provides 4 copies of CPU clock, 6 copies of PCI clock, two system clocks, one 24Mhz and one 48Mhz clock. n Support 32Mhz Asynchronous PCI BUS clock. n On chip loop filter ponents for dual PLLs. n 3.3V and 5V operation; 50 percent duty cycle. n Meets Intel Triton system clocking requirements n Available in 28 pin 300 mil SOIC. PIN INFORMATION DESCRIPTION The PLL52C59-14A is a high performance system clock generator designed to support Pentium/PCI based systems. Both synchronous and asynchronous mode for PCI BUS clock are provided. All output clocks skew and jitter performance are designed to be fully pliant with INTEL Pentium CPU timing requirements. TIMING SPECIFICATIONS PCLK-PCLK skew BCLK-BCLK skew PCLK-BCLK skew PCLK,BCLK slew rate PCLK Jitter <250 ps <500 ps 1~5 ns (PCLK leads) > 1 V/ns (0.4 ~2.4V) ±200 ps cycle-cycle BLOCK...