PLL601-01 Datasheet PDF - PhaseLink Low Phase Noise PLL Clock Multiplier Specs

PLL601-01 - Low Phase Noise PLL Clock Multiplier

Datasheet Summary

Description

The PLL601-01 is a low cost, high performance and low phase noise clock synthesizer.

With PhaseLink’s proprietary analog and digital Phase Locked Loop techniques, the chip accepts 10-27MHz crystal or clock input, and produces outputs clocks up to 160MHz at 3.3V.

Features

e h.
Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 10-27MHz fundamental crystal or.
Reference a clock. . D crystal load capacitor: no external.
Integrated w load capacitor required. w.
Output clocks up to 160MHz at 3.3V. w.
Low phase noise.
Output Enable function tri-state outputs. Low jitter: Less than 60 ps cycle to cycle. Advanced, low power, sub-micron CMOS process. 3.3V op.

Datasheet Details

Part number	PLL601-01
Manufacturer	PhaseLink
File Size	196.55 KB
Description	Low Phase Noise PLL Clock Multiplier
Datasheet	PLL601-01 Datasheet
Additional preview pages of the PLL601-01 datasheet.

📁 Similar Datasheet

PLL0210A - PHASE LOCKED LOOP (Z-Communications)

PLL0930A - PHASE LOCKED LOOP (Z-Communications)

PLL1000A - PHASE LOCKED LOOP (Z-Communications)

PLL102-03 - Low Skew Output Buffer (PhaseLink Corporation)

PLL102-04 - Low Skew Output Buffer (PhaseLink Corporation)

PLL102-05 - Low Skew Output Buffer (PhaseLink Corporation)

PLL102-10 - Low Skew Output Buffer (PhaseLink Corporation)

PLL102-108 - Programmable DDR Zero Delay Clock Driver (PhaseLink Corporation)

PLL102-109 - Programmable DDR Zero Delay Clock Driver (PhaseLink Corporation)

PLL102-15 - Low Skew Output Buffer (PhaseLink Corporation)

Full PDF Text Transcription

Click to expand full text

m o .c U 4 t e FEATURES e h • Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 10-27MHz fundamental crystal or • Reference a clock. .D crystal load capacitor: no external • Integrated w load capacitor required. w • Output clocks up to 160MHz at 3.3V. w• Low phase noise. • • • • • Output Enable function tri-state outputs. Low jitter: Less than 60 ps cycle to cycle. Advanced, low power, sub-micron CMOS process. 3.3V operation. Available in 16-Pin SOIC or TSSOP. Preliminary PLL601-01 Low Phase Noise PLL Clock Multiplier PIN CONFIGURATION CLK REFEN VDD VDD VDD 1 2 16 15 GND GND GND REFOUT OE S0 S3 S2 PLL 601-01 3 4 5 6 7 8 14 13 12 11 10 9 DESCRIPTIONS The PLL601-01 is a low cost, high performance and low phase noise clock synthesizer.

Published: Feb 10, 2006 |