PhaseLink PLL601-02
The PLL601-02 is a low cost, high performance and low phase noise clock synthesizer. With PhaseLink’s proprietary analog and digital Phase Locked Loop techniques, the chip accepts 10-27MHz crystal or clock input, and produces outputs clocks up to 160MHz at 3.3V.| Part No. | PLL601-02 |
|---|---|
| Datasheet | PLL601-02 Download |
| Manufacturer |  PhaseLink |
| Description | Low Phase Noise PLL Clock Multiplier |
| Buy | Stock & Price |
FEATURES
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● w w Full swing CMOS outputs with 25 mA drive capability at TTL levels. Reference 10-27MHz crystal or clock. Integrated crystal load capacitor: no external load capacitor required. Output clocks up to 160MHz at 3.3V. Low phase noise (-126dBc/Hz @ 1kHz). Output Enable function. Low jitter (RMS): 6.4ps (period), 9.4ps (accum.) Advanced low power sub-micron CMOS process. 3.3V operation. Available in 16-Pin SOIC or TSSOP. .D at h S a t e e 4U . m o c Preliminary PLL601-02 Low Phase Noise PLL Clock Multiplier PIN CONFIGURATION CLK REFEN VDD VDD VDD XOUT S1 XIN 1 2 16 15 GND GND GND REFOUT OE S0 S3 PLL 601-02 3 4 5 6 7 14 13 12 11 10 9 DESCRIPTIONS Ideal for 155.52MHz applications. MULTIPLIER SELECT TABLE BLOCK DIAGRAM S3 S1 S0 ROM Based Multipliers w w w .D t a S a e h S3 0 0 0 0 1 1 1 1 t e S1 0 0 1 1 0 0 1 1 U 4 8 .c m o GND S0 0 1 0 1 0 1 0 1 CLK Test Reserved 4x Input (Low Frequency VCO*) 8x Input (Low Frequency VCO*) Reserved XO Frequency Pass through 4x I...
