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PLL601-15 - Low Phase Noise PLL Clock Multiplier

Datasheet Summary

Description

The PLL601-15 is a low cost, high performance and low phase noise clock synthesizer.

It implements PhaseLink’s proprietary analog and digital Phase Locked Loop techniques for a fixed 5x multiplier.

Features

  • e h.
  • Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 20-30MHz crystal or clock.
  • Reference a.
  • Integrated crystal load capacitor: no external . D load capacitor required. w.
  • Output clocks up to 150MHz at 3.3V. w.
  • Low phase noise (-126dBc/Hz @ 1kHz). w.
  • Output Enable function.
  • Preliminary PLL601-15 Low Phase Noise PLL Clock Multiplier PIN.

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Datasheet preview – PLL601-15

Datasheet Details

Part number PLL601-15
Manufacturer PhaseLink
File Size 102.81 KB
Description Low Phase Noise PLL Clock Multiplier
Datasheet download datasheet PLL601-15 Datasheet
Additional preview pages of the PLL601-15 datasheet.

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Full PDF Text Transcription

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m o .c U 4 t e FEATURES e h • Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 20-30MHz crystal or clock. • Reference a • Integrated crystal load capacitor: no external .D load capacitor required. w • Output clocks up to 150MHz at 3.3V. w • Low phase noise (-126dBc/Hz @ 1kHz). w• Output Enable function. • • • • Preliminary PLL601-15 Low Phase Noise PLL Clock Multiplier PIN CONFIGURATION XIN GND GND GND 1 2 3 4 8 7 6 5 XOUT VDD VDD CLK Low jitter (RMS): 6.4ps (period), 9.4ps (accum.) Advanced low power sub-micron CMOS process. 3.3V operation. Available in 8-Pin SOIC or TSSOP. DESCRIPTIONS The PLL601-15 is a low cost, high performance and low phase noise clock synthesizer.
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