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PLL602-03 - Low Phase Noise CMOS XO

General Description

The PLL602-03 is a low cost, high performance and low phase noise XO, providing less than -130dBc at 10kHz offset in the 48MHz to 100MHz operating range.

The very low jitter (7 ps to 9 ps RMS period jitter) makes this chip ideal for applications requiring reference frequency sources.

Key Features

  • PIN.

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Datasheet Details

Part number PLL602-03
Manufacturer PhaseLink
File Size 94.44 KB
Description Low Phase Noise CMOS XO
Datasheet download datasheet PLL602-03 Datasheet

Other Datasheets by PhaseLink

Part Number Description
PLL602-00 Multiplier XO IC Die
PLL602-01 Low Phase Noise XO
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PLL602-11 Low Phase Noise PECL XO
PLL602-12 Low Phase Noise LVDS XO
PLL602-13 Low Phase Noise PECL XO
PLL602-14 Low Phase Noise LVDS XO
PLL602-35 (PLL602-35/37/38/39) Low Phase Noise Multiplier XO
PLL602-37 (PLL602-35/37/38/39) Low Phase Noise Multiplier XO

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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m Preliminary for proposal PLL602-03 o c . Low Phase Noise CMOS XO (48MHz to 100MHz) U t4 e FEATURES PIN CONFIGURATION e h XO output for the 48MHz to • Low phase noise S 100MHz range ta (-130 dBc at 10kHz offset). • CMOS a output. • 12 to .D25MHz crystal input. • Integrated crystal load capacitor: no external w load capacitor required. w • Low jitter (RMS): 7-9ps period jitter (1 sigma). w• 3.3V operation. CLK 1 2 3 4 8 7 6 5 GND PLL602-03 VDD OE GND N/C • Available in 8-Pin TSSOP or SOIC. DESCRIPTIONS The PLL602-03 is a low cost, high performance and low phase noise XO, providing less than -130dBc at 10kHz offset in the 48MHz to 100MHz operating range. The very low jitter (7 ps to 9 ps RMS period jitter) makes this chip ideal for applications requiring reference frequency sources.