PhaseLink PLL650-03
The PLL650-03 provides selectable spread spectrum modulation and selectable output frequencies. These pins allow 3 levels for input selection: namely, 0 (Connect to GND), 1 (Connect to VDD), M (Do not connect). In order to reduce pin usage, the PLL650-03 uses tri-level input pins.| Part No. | PLL650-03 |
|---|---|
| Datasheet | PLL650-03 Download |
| Manufacturer |  PhaseLink |
| Description | Low EMI Network LAN Clock |
| Buy | Stock & Price |
FEATURES
e h● Full CMOS output swing with 40-mA output drive S output capability. 25-mA drive at TTL level. a t
● Advanced, low power, sub-micron CMOS processes. a
● 25MHz .D fundamental crystal or clock input.
● 4 outputs fixed at 50MHz with output disable, 1 output w selectable at 25MHz or 100MHz with output disable w
● SDRAM selectable frequencies of 66.6, 75, 83.3, 100MHz w (Double Drive Strength).
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● PLL650-03 Low EMI Network LAN Clock PIN CONFIGURATION XIN XOUT/50MHz_OE*^ GND VDD 1 2 16 15 VDD VDD 25MHz/100MHz GND GND SDRAMx2 VDD 50MHz/SS0* T PLL 650-03 3 4 5 6 7 8 14 13 12 11 10 9 Spread spectrum technology selectable for EMI reduction from ±0.5%, ±0.75% center for SDRAM and CPU. Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 16-Pin 150mil SOIC. DESCRIPTIONS The PLL 650-03 is a low cost, low jitter, and high performance clock synthesizer. With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25.0 MHz crystal, and produces multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs.
