PhaseLink PLL650-05
The PLL650-05 provides selectable spread spectrum modulation and selectable output frequencies. These pins allow 3 levels for input selection: namely, 0 (Connect to GND), 1 (Connect to VDD), M (Do not connect). In order to reduce pin usage, the PLL650-05 uses tri-level input pins.| Part No. | PLL650-05 |
|---|---|
| Datasheet | PLL650-05 Download |
| Manufacturer |  PhaseLink |
| Description | Low EMI Network LAN Clock |
| Buy | Stock & Price |
FEATURES
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● Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 3 fixed outputs of 25MHz, 75Mhz and 125Mhz with output disable SDRAM selectable frequencies of 105, 83.3, 140MHz (Double Drive Strength). Spread spectrum technology selectable for EMI reduction from ±0.5%, ±0.75% center for SDRAM and CPU. Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 16-Pin 150mil SOIC. .D at h S a t e e 4U . m o c PLL650-05 Low EMI Network LAN Clock PIN CONFIGURATION XIN XOUT/ENB_125M*^ GND VDD 125MHz GND 75MHz/FS1*^ ENB_75MHz^ 1 2 16 15 VDD VDD 25MHz/FS0*^ GND GND SDRAMx2 VDD SS0T PLL 650-05 3 4 5 6 7 8 14 13 12 11 10 9 Note: SDRAMx2: Double Drive strength. T: Tri-Level input ^: Internal pull-up resistor *: Bi-directional pin (input value is latched upon power-up). DESCRIPTIONS The PLL 650-05 is a low cost, low jitter, and high performance clock synthesizer.
