PLL650-05 Datasheet | PhaseLink

Features - - - - w w- - - - - w - Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 3 fixed outputs of 25MHz, 75Mhz and 125Mhz with output disable SDRAM selectable frequencies of 105, 83.3, 140MHz (Double Drive Strength). Spread spectrum technology selectable for EMI reduction from ±0.5%, ±0.75% center for SDRAM and CPU. Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 16-Pin 150mil SOIC. .D at h S a t e e 4U . m o c Low EMI Network LAN Clock PIN CONFIGURATION XIN XOUT/ENB_125M- ^ GND VDD...