PhaseLink PLL650-07
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL650-07 S C PART NUMBER TEMPERATURE C=COMMERCIAL M=MILITARY I=INDUSTRIAL PACKAGE TYPE S=SOIC PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable.FEATURES
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● w w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 2 outputs fixed at 50MHz, 2 outputs fixed at 25MHz . Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 14-Pin 150mil SOIC. .D at h S a t e e 4U . m o c PRELIMINARY PLL650-07 LOW COST Network LAN Clock SOURCE PIN CONFIGURATION XOUT GNDA VDD50M 50MHz GND50M 50MHz VDD25M 1 2 14 13 XIN VDDA NC GND 25MHz GND25M 25MHz PLL 650-07 3 4 5 6 7 12 11 10 9 8 DESCRIPTIONS The PLL 650-07 is a low cost, low jitter, and high performance clock synthesizer. With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25.0 MHz crystal, and produces multiple output clocks for networking chips, and ASICs. BLOCK DIAGRAM XIN XOUT XTAL OSC w w w .D t a S a Charge Pump + Loop Filter e h VCO t e U 4 .c m o Phase Detector Post Divider 2...