PLL701-15 Overview
( 33 ~ 90MHz ) Buffered Clock Output. 1X the input frequency ( FIN ). 1X the input frequency ( FIN.
PLL701-15 Key Features
- cycle jitter. ± 0.50% Center Spread Modulation. TTL/CMOS patible outputs. 3.3V operation. Available in 8-Pin 150mil SOIC