PhaseLink PLL702-03
the PLL702-02 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 = Connect to GND, 1 = Connect to VDD, M = Do not connect.| Part No. | PLL702-03 |
|---|---|
| Datasheet | PLL702-03 Download |
| Manufacturer |  PhaseLink |
| Description | Low EMI Peripheral Clock Generator |
| Buy | Stock & Price |
FEATURES
PIN ASSIGNMENT e h● Single Low EMI IC to replace multiple crystals and S oscillators on Notebooks and Motherboards (27MHz, a t 24.576MHz, 25MHz). 8MHz, 12MHz, a
● Single crystal input: 24.576MHz (accuracy requirement D . +/- 20ppm)
● w than 10ppm Frequency Synthesis error, meeting wLess AC97, IEEE1394, IEEE802 and USB2.0 frequency w precision specification. VDDOSC XIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDDB2 27MHz PLL 702-03 XOUT VSSB2 8MHz
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● 27MHz clock with 5 levels of Selectable Spread Spectrum modulation form +/- 0.5% to +/- 1.5% center. 25MHz clock with double drive strength (Ethernet PHY and MAC). 24.576MHz clocks for Audio Codec and IEEE1394. Selectable 12MHz (USB 2.0) or 8MHz (Keyboard controller). Dual power source selection for 24.576MHz, 8MHz, and 12MHz. Available in 16-Pin SOIC or TSSOP. Table 1. SPREAD SPECTRUM SELECTION SST1 1 1 1 0 0 0 SST0 1 0 M 1 0 M SST Modulation only on 27MHz. (pin 15) +/- 1.5 % +/- 1 % Notes: M = Do not connect. 1 = Pulled up.
