Philips 74ALVC04
The 74ALVC04 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74ALVC04 provides six inverting buffers.| Part No. | 74ALVC04 |
|---|---|
| Datasheet | 74ALVC04 Download |
| Manufacturer |  Philips |
| Description | Hex inverter |
| Buy | Stock & Price |
FEATURES
● Wide supply voltage range form 1.65 to 3.6 V● 3.6 V tolerant inputs/outputs
● CMOS low power consumption
● Direct interface with TTL levels (2.7 to 3.6 V)
● Power-down mode
● Latch-up performance exceeds 250 mA
● Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).
● ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. The 74ALVC04 provides six inverting buffers. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL PARAMETER tPHL/tPLH propagation delay nA to nY CI input capacitance CPD power dissipation capacitance per buffer CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ VCC = 2.5 V; CL = 30 pF; RL = 500 Ω VCC = 2.7 V; CL = 50 pF; RL = 500 Ω VCC = 3.3 V; CL = 50 pF; RL = 500 Ω VCC = 3.3 V; notes 1 and 2 TYPICAL UNIT 2.4 ns 1.8 ns 2.3 ns 2.0 ns 3.5 pF 26 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW).
