74F224 Datasheet PDF

Philips 74F224

the 74F224 can be easily expanded in multiples of 15m+1 words or of 4n bits, or both (where n is the number of packages in the horizontal array). For longer words using 74F224, the IR signals of the first-rank packages and OR signals of the last-rank packages must be ANDed for proper synchronization.The 3-State outputs controlled by a single input (OE) make bus connection and multiplexing easy.

Part No.	74F224
Datasheet	74F224 Download
Manufacturer	Philips
Description	16 4 Synchronous FIFO
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FEATURES

outputs
● Independent synchronous inputs and
● Organized as 16 words of 4 bits
● DC to 50MHz data rate
● 3-State outputs
● Cascadable in word–width and depth direction TYPICAL SUPPLY CURRENT (TOTAL) 90mA

DESCRIPTION

This 64-bit active element First-In-First-Out (FIFO) is a monolithic Schottky-clamped transistor-transistor logic (STLL) array organized as 16 words of 4-bits each. A memory system using However, an external gating is required (see Figure 1). TYPE TYPICAL fmax 50MHz 74F224 ORDERING INFORMATION ORDER CODE

DESCRIPTION

COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 16-pin plastic Dual In-line Package 16-pin plastic Small Outline Large N74F224N N74F224D 0406C 0171B DRAWING NUMBER INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS LDCP D0 – D3 OE UNCP MR IR Q0 – Q3 Load clock input Data inputs Output enable input (active high) Unload clock input Master reset input (active low) Input ready output Data outputs

DESCRIPTION

74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/...