74F2373 Datasheet | Philips Semiconductors

FEATURES - 8-bit transparent latch - 30 Ohm output termination for driving DRAM - 3-State outputs glitch free during power-up and power-down - mon 3-State output register - Independent register and 3-State buffer operation DESCRIPTION The 74F2373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The 30 Ohm series termination on the outputs reduces over/undershoot, making them ideal for driving DRAM The data on the D inputs is transferred to the latch outputs when the enable (E) input is high. The latch remains transparent to the data input while E is high, and stores the data that is present one setup time before the high-to-low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is low, latched or transparent data appears at the output. When OE is high, the outputs are in high impedance “off ” state, which means they will neither drive nor load the bus. TYPICAL PROPAGATION DELAY 4.5ns TYPICAL SUPPLY CURRENT (TOTAL) 35m A TYPE 74F2373 ORDERING INFORMATION ORDER CODE DESCRIPTION MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 20-pin plastic DIP 20-pin plastic SOL N74F2373N N74F2373D SOT146-1 SOT163-1 DRAWING NUMBER INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS D0 - D7 E OE Q0 - Q7 Data inputs Enable input (active high) Output enable inputs (active low) 3-State outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 150/40 LOAD VALUE HIGH/LOW 20µA/0.6m A 20µA/0.6m A 20µA/0.6m A 3.0m A/3.0m A NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6m A in the low state. PIN CONFIGURATION OE 1 Q0 2 D0 3 D1 4 Q1 5 Q2 6 D2 7 D3 8 Q3 9 GND 10 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 E LOGIC SYMBOL 3 4...