74F2952 Datasheet | Philips Semiconductors

FEATURES 74F2952, 74F2953 Registered transceiver, non-inverting (3-State) Registered transceiver, inverting (3-State) DESCRIPTION The 74F2952 and 74F2953 are 8-bit registered transceivers. Two 8-bit back-to-back registers store data flowing in both directions between two bi-directional buses. Data applied to the inputs is entered and stored on the rising edge of the Clock (CPXX) provided that the Clock Enable (CEXX) is Low. The data is then present at the 3-State output buffers, but is only accessible when the Output Enable (OEXX) is Low. Data flow from ‘A’ inputs to ‘B’ outputs is the same as for ‘B’ inputs to ‘A’ outputs. TYPICAL SUPPLY CURRENT (TOTAL) 105m A 105m A - 8-bit registered transceivers - Two 8-bit, back-to-back registers store data moving in both directions between two bidirectional buses - Separate Clock, Clock Enable and 3-State Enable provided for each register - 74F2952 non-inverting - 74F2953 inverting - AM2952/2953 functional equivalent - ‘A’ outputs sink 24m A and source 3m A - ‘B’ outputs sink 64m A and source 15m A - 300 mil wide 24-pin Slim DIP package ORDERING INFORMATION DESCRIPTION 24-pin Plastic Slim DIP (300mil) 24-pin Plastic SOL1 TYPE 74F2952 74F2953 TYPICAL f MAX 160MHz 160MHz MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F2952N, N74F2953N N74F2952D, N74F2953D N74F2952A, N74F2953A PACKAGE DRAWING NUMBER SOT222-1 SOT137-1 SOT261-2 28-pin Plastic Leaded Chip Carrier NOTE: 1. Thermal mounting techniques are remended. See SMD Process Applications for a discussion of thermal consideration for surface mounted devices. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS A0 - A7 B0 - B7 CPAB, CPBA CEAB, CEBA OEAB, OEBA A0 - A7 B0 - B7 DESCRIPTION Port A, 3-State inputs Port B, 3-State inputs Clock inputs Clock Enable inputs Output Enable inputs Port A, 3-State outputs Port B, 3-State outputs 74F(U.L.) HIGH/LOW 3.5/1.0 3.5/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 750/106.7 LOAD VALUE HIGH/LOW 70µA/0.6m A 70µA/0.6m A 20µA/0.6m A 20µA/0.6m A...