74F350 Datasheet | Philips Semiconductors

FEATURES select lines - Shifts 4 bits of data to 0, 1, 2, 3 places under control of two - 3-State outputs for bus organized systems DESCRIPTION The 74F350 is a bination logic circuit that shifts a 4-bit word from 0 to 3 places. No clocking is required as with shift registers. The 74F350 can be used to shift any number of bits any number of places up or down by suitable interconnection. Shifting can be: 1. Logical - with logic zeros filled in at either end of the shifting field. 2. Arithmetic - where the sign bit is extended during a shift down. 3. End around - where the data word forms a continuous loop. The 3-State outputs are useful for bus interface applications or expansion to a larger number of shift positions in end around shifting. The active Low Output Enable (OE) controls the state of the outputs. The outputs are in the high impedance “off” state when OE is High, and they are active when OE is Low. PIN CONFIGURATION I- 3 I- 2 I- 1 I0 I1 I2 I3 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Y0 Y1 OE Y2 Y3 S0 S1 SF00205 ORDERING INFORMATION DESCRIPTION 16-pin plastic DIP 16-pin plastic SO MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F350N N74F350D TYPE 74F350 TYPICAL PROPAGATION DELAY 5.2ns TYPICAL SUPPLY CURRENT (TOTAL) 24m A INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS I- n, In S0, S1 OE Y0 - Y3 Data inputs Select inputs (active Low) Output Enable input (active Low) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/2.0 1.0/2.0 1.0/2.0 150/40 LOAD VALUE HIGH/LOW 20µA/1.2m A 20µA/1.2m A 20µA/1.2m A 3.0m A/24m A NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6m A in the Low state. LOGIC SYMBOL 1 2 3 4 5 6 7 IEC/IEEE SYMBOL D MUX 10 9 13 I- 3 I- 2 I- 1 I0 I1 I2 I3 10 11 12 13 11 12 13 14 12 13 14 15 13 14 15 16 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 0 1 EN G 0 [SHIFTER] 3 9 10 13 S1 S0 OE Y0 Y1 Y2 Y3 2 3 15 14 12 11 4 5 Z11 Z12 Z13 Z14 Z15 Z16 1 Z10 ≥1 ≥1 VCC = Pin 16 GND = Pin 8 ≥1 SF00206 6...