74F378 Description
The 74F378 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The mon buffered Clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge-triggered.
74F378 Key Features
- 6-bit high-speed parallel register
- Positive edge-triggered D-type inputs
- Fully buffered mon Clock and Enable inputs
- Input clamp diodes limit high speed termination effects
- Fully TTL and CMOS patible