74F579 Datasheet | Philips Semiconductors

FEATURES - Fully synchronous operation - Multiplexed 3-State I/O ports for bus oriented applications - Built in cascading carry capability - U/D pin to control direction of counting - Separate pins for Master reset and Synchronous operation - Center power pins to reduce effects of package inductance - Count frequency 115MHz Typ - Supply current 100m A Typ - See 74F269 for 24-pin separate I/O port version - See 74F779 for 16-pin version DESCRIPTION The 74F579 is a fully synchronous 8-stage Up/Down Counter with multiplexed 3-State I/O ports for bus-oriented applications. It features a preset capability for programmable operation, carry look-ahead for easy cascading and a U/D input to control the direction of counting. All state changes, except for the case of asynchronous reset, are initiated by the rising edge of the clock. TC output is not remended for use as a clock or asynchronous reset due to the possibility of decoding spikes. PIN CONFIGURATION CP I/O0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 MR SR CEP CET VCC TC U/D PE CS OE SF01085 ORDERING INFORMATION TYPE 74F579 TYPICAL f MAX 115MHz TYPICAL SUPPLY CURRENT (TOTAL) 100m A ORDERING INFORMATION DESCRIPTION 20-Pin Plastic DIP 20-Pin Plastic SOL MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F579N N74F579D PKG DWG # SOT146-1 SOT163-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS Data Inputs I/On PE U/D MR SR CEP CET CS OE CP TC Data Outputs Parallel Enable input (active Low) Up/Down count control input Master Reset input (active Low) Synchronous Reset input (active Low) Count Enable Parallel input (active Low) Count Enable Trickle input (active Low) Chip Select input (active Low) Output Enable input (active Low) Clock input (active Rising Edge) Terminal Count Output (active Low) DESCRIPTION 74F(U.L.) HIGH/LOW 3.5/1.0 150/40 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 70µA/0.6m A 3.0m A/24m A 20µA/0.6m A...