74F623 Datasheet | Philips Semiconductors

FEATURES 74F620/74F623 - High-impedance NPN base inputs for reduced loading (70µA in High and Low states) bus loading Enable inputs (OEBA and OEAB). The Enable inputs can be used to disable the device so that the buses are effectively isolated. The dual-enable configuration gives the 74F620 and 74F623 the capability to store data by the simultaneous enabling of OEBA and OEAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of the bus lines are at high impedance, both sets of bus lines (16 in all) will remain in their last states. TYPICAL PROPAGATION DELAY 3.5ns 4.5ns TYPICAL SUPPLY CURRENT (TOTAL) 80m A 105m A - Ideal for applications which require high output drive and minimal - Octal bidirectional bus interface - 3-State buffer outputs sink 64m A and source 15m A - 74F620, inverting - 74F623, non-inverting DESCRIPTION The 74F620 is an octal transceiver featuring inverting 3-State bus-patible outputs in both send and receive directions. The outputs are capable of sinking 64m A and sourcing up to 15m A, providing very good capacitive drive characteristics. The 74F623 is a non-inverting version of the 74F620. These octal bus transceivers are designed for asynchronous two-way munication between data buses. The control function implementation allows for maximum flexibility in timing. These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the TYPE 74F620 74F623 ORDERING INFORMATION DESCRIPTION 20-pin plastic DIP 20-pin plastic SOL MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F620N, N74623N N74F620D, N74623D PKG DWG # SOT146-1 SOT163-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS A0 - A7, B0 - B7 OEBA, OEAB A0 - A7 B0 - B7 Data inputs Output Enable inputs Data outputs Data outputs DESCRIPTION 74F(U.L.) HIGH/LOW 3.5/1.16 1.0/0.033 150/40 750/106.7 LOAD VALUE HIGH/LOW 70µA/70µA...