• Part: 74F777
  • Description: Triple bidirectional latched bus transceiver
  • Manufacturer: Philips Semiconductors
  • Size: 98.48 KB
Download 74F777 Datasheet PDF
Philips Semiconductors
74F777
74F777 is Triple bidirectional latched bus transceiver manufactured by Philips Semiconductors.
INTEGRATED CIRCUITS 74F777 Triple bidirectional latched bus transceiver (3-State + open collector) Product specification IC15 Data Handbook 1992 May 19 Philips Semiconductors Philips Semiconductors Product specification Triple bidirectional latched bus transceiver (3- State + Open Collector) Features - Latching transceiver - High drive Open Collector output current with minimum output swing range of 20 to 50 ohms and is terminated on each end with a 30 to 40 ohm resistor. The 74F777 is a triple bidirectional transceiver with Open Collector B and 3- State A port output drivers. A latch function is provided for the A port signals. The B port output driver is designed to sink 100m A from 2 volts to minimize crosstalk and ringing on the bus. A separate output threshold clamp voltage (VX) is provided to prevent the A port output High level from exceeding future high density processor supply voltage levels. For 5 volt systems, VX is simply tied to VCC. TYPE 74F777 TYPICAL PROPAGATION DELAY 7.0ns TYPICAL SUPPLY CURRENT( TOTAL) 45m A - patible with Test Mode (TM) bus specification - Controlled output ramp - Multiple package options - Industrial temperature range available (- 40°C to +85°C) DESCRIPTION The 74F777 is a triple bidirectional latched bus transceiver and is intended to provide the electrical interface to a high performance wired- OR bus. This bus has a loaded characteristics impedance ORDERING INFORMATION ORDER CODE DESCRIPTION MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 20- pin plastic DIP (300 mil) 20- pin PLCC N74F777N N74F777A INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = - 40°C to +85°C I74F777N I74F777A SOT146-1 SOT380-1 PKG DWG # INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS A0 - A2 B0 - B2 OEA0 - OEA2 OEB0 - OEB2 LE0 - LE2 A0 - A2 PNP latched inputs Data inputs with threshold circuitry A output enable inputs (active- High) B output enable inputs (active- Low) Latch enable inputs (active- Low) 3- State outputs DESCRIPTION 74F (U.L.) HIGH/LOW...