74F85 Datasheet | Philips Semiconductors

FEATURES - High-impedance NPN base inputs for reduced loading (20µA in High and Low states) PIN CONFIGURATION B3 IA<B IA=B IA>B 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC A3 B2 A2 A1 B1 A0 B0 - Magnitude parison of any binary words - Serial or parallel expansion without extra gating DESCRIPTION The 74F85 is a 4-bit magnitude parator that can be expanded to almost any length. It pares two 4-bit binary, BCD, or other monotonic codes and presents the three possible magnitude results at the outputs. The 4-bit inputs are weighted (A0- A3) and (B0- B3) where A3 and B3 are the most significant bits. The operation of the 74F85 is described in the Function Table, showing all possible logic conditions. The upper part of the table describes the normal operation under all conditions that will occur in a single device or in a series expansion scheme. In the upper part of the table the three outputs are mutually exclusive. In the lower part of the table, the outputs reflect the feed-forward conditions that exist in the parallel expansion scheme. The expansion inputs IA>B, and IA=B and IA<B are the least significant bit positions. When used for series expansion, the A>B, A=B and A<B outputs of the lease significant word are connected to the corresponding IA>B, IA=B and IA<B inputs of the next higher stage. Stages can be added in this manner to any length, but a propagation delay penalty of about 15ns is added with each additional stage. For proper operation, the expansion inputs of the least significant word should be tied as follows: IA>B = Low, IA=B = High, and IA<B = Low. A>B A=B A<B GND SF00075 TYPE TYPICAL PROPAGATION DELAY 7.0ns TYPICAL SUPPLY CURRENT (TOTAL) 40m A ORDERING INFORMATION DESCRIPTION 16-pin plastic DIP 16-pin plastic SO MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F85N N74F85D PKG DWG # SOT38-4 SOT162-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS A0- A3 B0- B3 IA<B, IA=B, IA>B A<B, A=B, A>B DESCRIPTION paring inputs paring inputs...