74F863 Datasheet | Philips Semiconductors

FEATURES - Provide high performance bus interface buffering for wide data/address paths or buses carrying parity ORDERING INFORMATION PACKAGES 24-pin Plastic Slim Dual In-line (300mil) Package 24-pin Plastic Small Outline Large1 MERCIAL RANGE VCC = 5V±10%; Ta = 0°C to +70°C N74F862N, N74F863N PKG DWG # - High impedance NPN base inputs for reduced loading (20µA in High and Low states) - IIL is 20µA vs. 1000µA for AM29861 series - Buffered control inputs for light loading, or increased fan-in as required with MOS microprocessors SOT222-1 N74F862D, N74F863D SOT137-1 - Positive and negative over-shoots are clamped to ground - 3-State outputs glitch free during power-up and power-down - Slim dual In-line (DIP) 300mil package - Broadside pinout patible with AMD AM29862- 29863 - Outputs sink 64m A DESCRIPTION The 74F862 and 74F863 bus transceivers provide high performance bus interface buffering for wide data/address paths of buses carrying parity. The 74F863 9-bit bus transceiver has NOR-ed transmit and receive output enables for maximum control flexibility. TYPICAL PROPAGATION DELAY 6.0ns 6.0ns TYPICAL SUPPLY CURRENT (TOTAL) 150m A 115m A NOTE: 1. Thermal mounting techniques are remended. See SMD Process Applications for a discussion of thermal considerations for surface mounted devices. PIN CONFIGURATION OEBA A0 A1 A2 A3 A4 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 OEAB TYPE 74F862 74F863 A5 A6 A7 A8 A9 GND TOP VIEW SF00518 2000 Mar 24 853-0881 23378 Philips Semiconductors Product specification Bus transceivers (3-State) 74F862, 74F863 PIN CONFIGURATION 74F862 OEBA A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 GND 1 2 3 4 5 6 7 8 9 10 11 12 TOP VIEW 24 23 22 21 20 19 18 17 16 15 14 13 VCC B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 OEAB PIN CONFIGURATION OEBA0 A0 A1 A2 A3 A4 A5 A6 A7 A8 OEBA1 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC B0 B1 B2 B3 B4 B5 B6 B7 B8 OEAB0 OEAB1 SF00521 TOP...