74HC258 Datasheet | Philips Semiconductors

FEATURES - Inverting data path - 3-state outputs interface directly with system bus - Output capability: bus driver - ICC category: MSI. GENERAL DESCRIPTION The 74HC/HCT258 are high-speed Si-gate CMOS devices and are pin patible with Low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT258 have four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two sources and are controlled by a mon data select input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data inputs from source 1 (1I1 to 4I1) are selected when S is HIGH. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. 1Y = OE × ( 1I 1 × S + 1I 0 × S ) 2Y = OE × ( 2I 1 × S + 2I 0 × S ) 3Y = OE × ( 3I 1 × S + 3I 0 × S ) 4Y = OE × ( 4I 1 × S + 4I 0 × S ) 74HC/HCT258 Data appears at the outputs (1Y to 4Y) in inverted form from the select inputs. The ‘258’ is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high impedance OFF-state when OE is HIGH. The logic equations for the outputs are: The ‘258’ is identical to the ‘257’ but has inverting outputs. TYPICAL SYMBOL t PHL/t PLH PARAMETER propagation delay n I0, n I1 to n Y S to n Y CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in p F; VCC = supply voltage in Volts. 2. For HC the condition is VI = GND to VCC; For HCT the condition is VI = GND to VCC - 1.5 V. input capacitance power dissipation capacitance per multiplexer notes 1 and 2 CONDITIONS HC CL = 15 p F; VCC = 5 V 9 14 3.5 55 13 16 3.5 38 HCT ns ns p F p F UNIT 1999 Sep 02 Philips Semiconductors Product specification Quad 2-input multiplexer; 3-state;...