74HC297 Datasheet | Philips Semiconductors

FEATURES - Digital design avoids analog pensation errors - Easily cascadable for higher order loops - Useful frequency range: - DC to 55 MHz typical (K-clock) - DC to 35 MHz typical (I/D-clock) - Dynamically variable bandwidth - Very narrow bandwidth attainable - Power-on reset - Output capability: standard/bus driver - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT297 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT297 are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. These devices contain all the necessary circuits, with the exception of the divide-by-n counter, to build first order phase-locked-loops. Both EXCLUSIVE-OR (XORPD) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range. Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Fig.7) or to cascade to higher order phase-locked-loops. The length of the up/down K-counter is digitally programmable according to the K-counter function table. With, A, B, C and D all LOW, the K-counter is disabled. With A HIGH and B, C and D LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and D are all programmed HIGH, the K-counter bees seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to D inputs can maximize the overall performance of the digital phase-locked loop. The “297” can perform the classic first-order phase-locked-loop function without using analog September 1993 2 74HC/HCT297...