Philips 74HC4518
The 74HC/HCT4518 are high-speed Si-gate CMOS devices and are pin compatible with the “4518” of the “4000B” series. They are specified in compliance with JEDEC standard no. The 74HC/HCT4518 are dual 4-bit internally synchronous BCD counters with an active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous master reset input (nMR).| Part No. | 74HC4518 |
|---|---|
| Datasheet | 74HC4518 Download |
| Manufacturer |  Philips |
| Description | Dual synchronous BCD counter |
| Buy | Stock & Price |
FEATURES
● Output capability: standard● ICC category: MSI
GENERAL DESCRIPTION
7A. The counter advances on either the LOW-to-HIGH transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1.APPLICATIONS
● Multistage synchronous counting● Multistage asynchronous counting
● Frequency dividers QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL PARAMETER CONDITIONS TYPICAL HC HCT tPHL/ tPLH tPHL fmax CI CPD propagation delay nCP0, nCP1 to nQn propagation delay nMR to nQn maximum clock frequency input capacitance power dissipation capacitance per counter CL = 15 pF; VCC = 5 V notes 1 and 2 20 13 61 3.5 29 24 14 55 3.5 27 UNIT ns ns MHz pF pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi...
