Philips 74HC597
The 74HC/HCT597 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. The 74HC/HCT597 consist each of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register.FEATURES
● 8-bit parallel storage register inputs● Shift register has direct overriding load and clear
● Output capability: standard
● ICC category: MSI
GENERAL DESCRIPTION
74HC/HCT597 7A. Both the storage register and the shift register have positive edge-triggered clocks. The shift register also has direct load (from storage) and clear inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay SHCP to Q STCP to Q PL to Q fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. maximum clock frequency SHCP input capacitance power...