74HC85 Datasheet | Philips Semiconductors

INTEGRATED CIRCUITS DATA SHEET For a plete data sheet, please also download: - The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications - The IC06 74HC/HCT/HCU/HCMOS Logic Package Information - The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT85 4-bit magnitude parator Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 4-bit magnitude parator Features - Serial or parallel expansion without extra gating - Magnitude parison of any binary words - Output capability: standard - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT85 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT85 are 4-bit magnitude parators that can be expanded to almost any length. They perform parison of two 4-bit binary, BCD or other monotonic codes and present the three possible magnitude results at the outputs (QA>B, QA=B and QA<B). The 4-bit inputs are QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT85 weighted (A0 to A3 and B0 to B3), where A3 and B3 are the most significant bits. The operation of the “85” is described in the function table, showing all possible logic conditions. The upper part of the table describes the normal operation under all conditions that will occur in a single device or in a series expansion scheme. In the upper part of the table the three outputs are mutually exclusive. In the lower part of the table, the outputs reflect the feed forward conditions that exist in the parallel expansion scheme. For proper pare operation the expander inputs (IA>B, IA=B and IA<B) to the least significant position must be connected as follows: IA<B = IA>B = = LOW and IA=B = HIGH. For words greater than 4-bits, units can be cascaded by connecting outputs QA<B, QA>Β and QA=B to the corresponding inputs of the significant parator. TYPICAL SYMBOL t...