74HCT158 Datasheet | Philips Semiconductors

FEATURES - Inverting data path - Output capability: standard - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT158 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT158 are quad 2-input multiplexers which select 4 bits of data from two sources and are controlled by a mon data select input (S). The four outputs present the selected data in the inverted form. The enable input (E) is active LOW. When E is HIGH, all the outputs (1Y to 4Y) are forced HIGH regardless of all other input conditions. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT158 Moving the data from two groups of registers to four mon output buses is a mon use of the “158”. The state of S determines the particular register from which the data es. It can also be used as a function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable mon. The ”158” is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The logic equations for the output are: 1Y = E.(1l1.S + 1l0.S) 2Y = E.(2l1.S + 2l0.S) 3Y = E.(3l1.S + 3l0.S) 4Y = E.(4l1.S + 4l0.S) The “158” is identical to the “157” but has inverting outputs. TYPICAL SYMBOL t PHL/ t PLH PARAMETER propagation delay n I0, n I1 to n Y E to n Y S to n Y CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. input capacitance power dissipation capacitance per...