74HCT160
Overview
- Synchronous counting and loading
- Two count enable inputs for n-bit cascading
- Positive-edge triggered clock
- Asynchronous reset
- Output capability: standard
- ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT160 are synchronous presettable decade counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable QUICK REFERENCE DATA GND = 0 V; Tamb= 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER tPHL propagation delay CP to Qn CP to TC MR to Qn MR to TC CET to TC propagation delay CP to Qn CP to TC CET to TC maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 39 34 pF CONDITIONS HC CL = 15 pF; VCC = 5 V 19 21 21 21 14 19 21 14 61 3.5 HCT 21 24 23 26 14 21 20 7 31 3.5 ns ns ns ns ns ns ns ns MHz pF UNIT Notes
