74HCT174 Datasheet | Philips Semiconductors

FEATURES - Six edge-triggered D-type flip-flops - Asynchronous master reset - Output capability: standard - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. 74HC/HCT174 The 74HC/HCT174 have six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The mon clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set-up time prior to the LOW-to-HIGH clock transition, is transferred to the corresponding output of the flip-flop. A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs. The device is useful for applications requiring true outputs only and clock and master reset inputs that are mon to all storage elements. QUICK REFERENCE DATA GND = 0 V; Tamb= 25 °C; tr = tf = 6 ns TYPICAL SYMBOL t PHL/ t PLH PARAMETER propagation delay CP to Qn MR to Qn fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V maximum clock frequency input capacitance power dissipation capacitance per flip-flop notes 1 and 2 CONDITIONS HC CL = 15 p F; VCC = 5 V 17 13 99 3.5 17 18 17 69 3.5 17 ns ns MHz p F p F HCT UNIT 1998 Jul 08 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger ORDERING INFORMATION TYPE NUMBER 74HC174N; 74HCT174N 74HC174D; 74HCT174D 74HC174DB; 74HCT174DB 74HC174PW; 74HCT174PW PACKAGE NAME DIP16 SO16 SSOP16 TSSOP16 DESCRIPTION plastic dual in-line package; 16 leads (300 mil); long body...