74HCT356 Datasheet | Philips Semiconductors

FEATURES - Non-transparent data latches - Transparent address latch - Easily expanding - plementary outputs - Output capability: bus driver - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT356 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL 74HC/HCT356 (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT356 data selectors/multiplexers contain full on-chip binary decoding, to select one-of-eight data sources. The data select address is stored in transparent latches that are enabled by a LOW on the latch enable input LE. Data on the 8 input lines (D0 to D7) is clocked into a edge-triggered data register by a LOW-to-HIGH transition of the clock (CP). When the output enable input OE1 = HIGH, OE2 = HIGH or OE3 = LOW, the outputs go to the high impedance OFF-state. Operation of these output enable inputs does not affect the state of the latches and register. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL t PHL/ t PLH PARAMETER propagation delay Sn, LE to Y, Y CP to Y, Y CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 p F; VCC = 5 V 24 20 3.5 123 25 22 3.5 125 ns ns p F p F HCT UNIT December 1990 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state PIN DESCRIPTION PIN NO. 8, 7, 6, 5, 4, 3, 2, 1 9 10 11 14, 13, 12 15, 16 17 18 19 20 SYMBOL D0 to D7 CP GND LE S0, S1, S2 OE1, OE2 OE3 Y Y VCC NAME AND FUNCTION data inputs 74HC/HCT356 clock input data...