74HCT4075 Datasheet | Philips Semiconductors

FEATURES - Output capability: standard - ICC category: SSI GENERAL DESCRIPTION The 74HC/HCT4075 are high-speed Si-gate CMOS devices and are pin patible with the “4075” of the “4000B” series. They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT4075 provide the 3-input OR function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL PARAMETER CONDITIONS t PHL/ t PLH CI CPD propagation delay n A, n B, n C to n Y input capacitance CL = 15 p F; VCC = 5 V power dissipation capacitance per gate notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V TYPICAL HC 8 3.5 28 HCT 10 3.5 32 UNIT ns p F p F ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 Philips Semiconductors Triple 3-input OR gate PIN DESCRIPTION PIN NO. 3, 1, 11 4, 2, 12 5, 8, 13 6, 9, 10 7 14 SYMBOL 1A to 3A 1B to 3B 1C to 3C 1Y to 3Y GND VCC NAME AND FUNCTION data inputs data inputs data inputs data outputs ground (0 V) positive supply voltage Product specification 74HC/HCT4075 Fig.1 Pin configuration. Fig.4 Functional diagram. December 1990 Fig.2 Logic symbol. Fig.3 IEC logic symbol. FUNCTION TABLE INPUTS OUTPUT n A n B n C LLL HXX XHX XXH n Y Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t...