Philips 74HCT4510
The 74HC/HCT4510 are high-speed Si-gate CMOS devices and are pin compatible with the “4510” of the “4000B” series. They are specified in compliance with JEDEC standard no. The 74HC/HCT4510 are edge-triggered synchronous up/down BCD counters with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (D0 to D3), four parallel outputs (Q0 to Q3), an active LOW terminal count output (TC), and an overriding asynchronous master reset input (MR).| Part No. | 74HCT4510 |
|---|---|
| Datasheet | 74HCT4510 Download |
| Manufacturer |  Philips |
| Description | BCD up/down counter |
| Buy | Stock & Price |
FEATURES
● Output capability: standard● ICC category: MSI
GENERAL DESCRIPTION
7A. Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all other input conditions except the MR input, which must be LOW. With PL LOW, the counter changes on the LOW-to-HIGH transition of CP if CE is LOW. UP/DN determines the direction of the count, HIGH for counting up, LOW for counting down. When counting up, TC is LOW when Q0 and Q3 are HIGH and CE is LOW. When counting down, TC is LOW when Q0 to Q3 and CE are LOW. A HIGH on MR resets the counter (Q0 to Q3 = LOW) independent of all other input conditions. Logic equation for terminal count: TC = CE . {(UP/DN) . Q0 . Q3+(UP/DN) . Q0 . Q1 . Q2 . Q3} QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL PARAMETER CONDITIONS TYPICAL HC HCT tPHL/ tPLH fmax CI CPD propagation delay CP to Qn maximum clock frequency input capacitance power dissipation capacitance per package CL = 15 pF; VCC = 5 V 21 57 3.5 notes 1 and 2 50 23 58 3.5 53 Notes 1.
