74HCT540 Datasheet | Philips Semiconductors

FEATURES - Inverting outputs - Output capability: bus driver - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT540 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT540 The 74HC/HCT540 are octal inverting buffer/line drivers with 3-state outputs. The 3-state outputs are controlled by the output enable inputs OE1 and OE2. A HIGH on OEn causes the outputs to assume a high impedance OFF-state. The “540” is identical to the “541” but has inverting outputs. TYPICAL SYMBOL t PHL/ t PLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PARAMETER propagation delay An to Yn input capacitance power dissipation capacitance per buffer notes 1 and 2 CONDITIONS HC CL = 15 p F; VCC = 5 V 9 3.5 39 HCT 11 3.5 44 ns p F p F UNIT December 1990 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting PIN DESCRIPTION PIN NO. 1, 19 2, 3, 4, 5, 6, 7, 8, 9 10 18, 17, 16, 15, 14, 13, 12, 11 20 SYMBOL OE1, OE2 A0 to A7 GND Y0 to Y7 VCC NAME AND FUNCTION 74HC/HCT540 output enable input (active LOW) data inputs ground (0 V) bus outputs positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting FUNCTION TABLE INPUTS OE1 L L X H Notes OE2 L L H X 74HC/HCT540 OUTPUT An L H X X Yn H L Z Z 1. H = HIGH voltage level L = LOW voltage level X = don’t care...