74HCT597 Datasheet | Philips Semiconductors

FEATURES - 8-bit parallel storage register inputs - Shift register has direct overriding load and clear - Output capability: standard - ICC category: MSI GENERAL DESCRIPTION 74HC/HCT597 The 74HC/HCT597 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT597 consist each of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shift register also has direct load (from storage) and clear inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL t PHL/ t PLH PARAMETER propagation delay SHCP to Q STCP to Q PL to Q fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. maximum clock frequency SHCP input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 p F; VCC = 5 V 17 25 21 96 3.5 29 20 29 26 83 3.5 32 ns ns ns MHz p F p F HCT UNIT December 1990 Philips Semiconductors Product specification 8-bit shift register with input flip-flops PIN DESCRIPTION PIN NO. 8 9 10 11 12 13 14 15, 1, 2, 3, 4, 5, 6, 7 16 SYMBOL GND Q MR SHCP STCP PL DS D0 to D7 VCC NAME AND FUNCTION ground (0 V) serial data output asynchronous reset input (active LOW) 74HC/HCT597 shift clock input (LOW-to-HIGH, edge-triggered) storage clock input (LOW-to-HIGH, edge-triggered) parallel load input (active LOW) serial data input parallel data inputs positive supply voltage Fig.1 Pin configuration. Fig.2 Logic...