74HCT640 Datasheet | Philips Semiconductors

FEATURES - Octal bidirectional bus interface - Inverting 3-state outputs - Output capability: bus driver - ICC category: MSI GENERAL DESCRIPTION 74HC/HCT640 The 74HC/HCT640 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT640 are octal transceivers featuring inverting 3-state bus patible outputs in both send and receive directions. The “640” features an output enable (OE) input for easy cascading and a send/receive (DIR) for direction control. OE controls the outputs so that the buses are effectively isolated. The “640” is similar to the “245” but has inverting outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL t PHL/ t PLH PARAMETER propagation delay An to Bn; Bn to An input capacitance input/output capacitance power dissipation capacitance per transceiver notes 1 and 2 CONDITIONS HC CL = 15 p F; VCC = 5 V 9 HCT 9 ns UNIT CI CI/O CPD Notes 3.5 10 35 3.5 10 35 p F p F p F 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. March 1988 Philips Semiconductors Product specification Octal bus transceiver; 3-state; inverting PIN DESCRIPTION PIN NO. 1 2, 3, 4, 5, 6, 7, 8, 9 10 19 20 SYMBOL NAME AND FUNCTION DIR A0 to A7 GND OE VCC direction control data inputs/outputs ground (0 V) data inputs/outputs output enable input (active LOW) positive supply voltage 74HC/HCT640 18, 17, 16, 15, 14, 13, 12, 11 B0 to B7 Fig.1 Pin configuration. Fig.2 Logic symbol. FUNCTION TABLE inputs OE L L H Note 1. H L X Z = HIGH voltage level = LOW voltage...